HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 274

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

6.2.12
The DMA priority control register (PCR), shared by channels 0, 1, 2, and 3, specifies channel
priority. When multiple channels request a DMA transfer, the channel given the highest priority
can use the bus. This register can be accessed only in byte units.
Bits 7–5: Reserved. These bits always read 0 and must be set to 0.
Bit 4 (BRC: Bus Release Condition): Specifies the condition for the SCA to release the bus
control obtained in either single-block transfer mode or chained-block transfer mode as follows.
BRC = 0: The SCA releases the bus control when all DMA transfer requests have been processed.
BRC = 1: The SCA releases the bus control when every DMAC channel has performed one DMA
Rev. 0, 07/98, page 258 of 453
DMA Priority Control Register (PCR)
transfer according to the priority specified by the PR2–PR0 bits (channel priority bits)
of PCR. In this case, a channel releases the bus control when it has performed one
DMA transfer, and the bus control is given to a channel that has not performed a DMA
transfer. Bus control is switched between channels according to the CCC bit (channel
change condition bit ) of PCR. The SCA also releases the bus when all DMA transfer
requests have been processed, even when not all DMAC channels have performed one
DMA transfer.
Note: Bits 7–5 are reserved. These bits always read 0 and must be set to 0.
Single-block
transfer mode
Chained-block
transfer mode
Read/Write
Initial value
Bus release condition
0:
1:
—
No DMA request issued
One DMA transfer performed
by each channel
—
7
0
—
6
—
0
—
—
5
0
BRC
R/W
4
0
CCC
Channel change condition
0:
1:
R/W
3
0
Per bus cycle
No DMA request issued by
the corresponding channel
PR2
R/W
2
0
Channel priority
PR1
R/W
1
0
PR0
R/W
0
0