HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 89

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

CPU Mode 1: The SCA latches the address on lines A
must remain low throughout the bus cycle. After the bus cycle ends, CS must go high (inactive).
Figure 3.10 shows the slave mode bus timing sequence in CPU mode 1.
Note:
CPU Mode 2: The SCA latches the address on lines A
active low. CS and AS must remain low throughout the bus cycle. After the bus cycle ends, they
must go high (inactive). Figure 3.11 shows the slave mode bus timing sequence in CPU mode 2.
Read cycle
If RD is low (active) at the falling clock edge in the T
the register specified by the address on the data bus on the rising clock edge between the T
and T
high (inactive), the cycle ends: the SCA then drives the WAIT output active high and lets the
data bus float. The read cycle can be extended by delaying the high transition of RD.
Write cycle
If WR is low (active) at the rising clock edge between the T
data on the data bus on the falling clock edge in the T
specified by the address. WR must remain low until the falling clock edge in the T
When WR is driven high (inactive), the cycle ends: the SCA drives the WAIT output active
high.
CLK
CS
RD
WAIT
D to D
(In)
A to A
WR
D to D
(Out)
0
0
0
State numbers do not match MPU state numbers.
4
states. RD must remain low until the falling clock edge in the T
7
7
7
Figure 3.10 Slave Mode Bus Timing Sequence in CPU Mode 1
T
1
Read cycle SCA
T
2
Register address
T
3
T
MPU
4
T
1
Output data
Write cycle MPU
T
2
0
1
Data latch point
to A
to A
3
2
T
state, and stores the data in the register
Register address
state, the SCA outputs the contents of
3
7
Input data
7
when CS is driven active low. CS
when CS and AS are both driven
2
T
and T
4
SCA
Rev. 0, 07/98, page 73 of 453
3
T
states, the SCA latches the
5
4
state. When RD goes
5
state.
3