HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 332

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

This register can specify only the high-order eight bits (A
remaining low-order 16 bits (A
64-Kbyte units.
When PABR0 is set to 00H, the boundary is at the top of the memory space.
Physical Address Boundary Register 1 (PABR1): Specifies the high-order eight bits of the
boundary address between PAM and the physical address high area (PAH). This address is the
lower limit address of PAH.
This register can specify only the high-order eight bits (A
remaining low-order 16 bits (A
64-Kbyte units.
When PABR1 is set to 00H, the boundary is at the top of the memory space.
Boundary Address Setting Examples: The memory space is usually divided into three areas:
PAL, PAM, and PAH, as shown in figure 8.1. The boundary between PAL and PAM (the high-
order eight bits of the lower limit address of PAM) is specified by PABR0, and that between PAM
and PAH (the high-order eight bits of the lower limit address of PAH) is specified by PABR1, in
64-Kbyte units. In the figure, PABR0 and PABR1 are set to 01H and 40H, respectively. In this
case, each memory area is specified as follows:
Rev. 0, 07/98, page 316 of 453
Bit name
Read/Write
Initial value
Bit name
Read/Write
Initial value
PB07 PB06 PB05 PB04 PB03 PB02 PB01 PB00
PB17 PB16 PB15 PB14 PB13 PB12 PB11 PB10
R/W
R/W
7
0
7
0
15
15
A
A
PAL/PAM boundary address (high-order 8 bits)
PAM/PAH boundary address (high-order 8 bits)
R/W
R/W
0
0
) are fixed to 0000H. Thus, each area is specified in
) are fixed to 0000H. Thus, each area is specified in
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
23
23
R/W
R/W
3
0
3
0
A
A
16
16
) of the boundary address; the
) of the boundary address; the
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0