HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 188

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

CDE0 = 1:
This register monitors the status of only the top stage of the receive status FIFO in CPU modes 0,
2, and 3, which is different from status register 2 (ST2). ST2 monitors the OR of the status of the
top and second stages of the receive status FIFO. This register is also characterized by its
capability of monitoring the presence/absence of data in the top stage of the receive buffer. As a
result, monitoring this register and current status register 1 (CST1) enables the user to determine
which data status has generated an interrupt, and whether or not the following data can be read by
word. For CST1, see section 5.2.26, MSCI Current Status Register 1 (CST1).
5.2.26
Current status register 1 (CST1) monitors the second stage of the MSCI's 32-stage status FIFO.
This register indicates whether or not data is in the second stage of the receive buffer, and if there
is any data, indicates the status of the data.
This register is reset under either of the following conditions:
No bit of this register generates an interrupt.
Rev. 0, 07/98, page 172 of 453
RX reset command
Channel reset command
System stop mode
Async
Byte sync
Bit sync HDLC
Read/Write
Initial value
Note: The bits marked with * are reserved. These bits always read 0.
MSCI Current Status Register 1 (CST1)
Indicates that data is in the top stage of the receive buffer
Data status in the second stage of the receive buffer
EOMC1
—
R
7
0
*
SHRTC1
PMPC1
—
R
6
0
*
ABTC1
PEC1
—
R
5
0
*
FRMEC1
RBITC1
—
R
4
0
*
OVRNC1
R
3
0
CRCEC1
—
R
2
0
*
—
1
–
0
*
Current data 1
0: No data exists
1: Data exists
CDE1
R
0
0