HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 279

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

EOT = 1: Terminates transfer
6.3.2
Descriptors and buffers in system memory for MSCI-to-memory chained-block transfer mode are
shown in figure 6.9.
The descriptor format for MSCI-to-memory chained-block transfer mode is the same as that
shown in figure 6.8. Detailed descriptions of these fields are given below.
Chain Pointer (CP) (16 Bits): Specifies the low-order 16 bits of the 24-bit start address of the
next descriptor. The high-order eight bits are specified by the chain pointer base (CPB). The
chain pointer value is loaded into the current descriptor address register (CDA) at buffer
switching.
Buffer Pointer (BP) (24 Bits): Specifies the start address of the buffer corresponding to the
descriptor. The BP value is loaded into the buffer address register (BAR) at the start of transfer or
at buffer switching.
Data Length (DL) (16 Bits): Specifies the data length in the buffer corresponding to the
descriptor in byte units.
Figure 6.9 Descriptors and Buffers in MSCI-to-Memory Chained-Block Transfer Mode
MSCI-to-Memory Chained-Block Transfer Mode (Reception)
Buffer pointer (BP) A (24 bits)
Chain pointer (CP) B (16 bits)
Buffer pointer (BP) B (24 bits)
Chain pointer (CP) A (16 bits)
Data length (DL) B (16 bits)
Data length (DL) A (16 bits)
Status (ST) A (8 bits)
Status (ST) B (8 bits)
Descriptor table
Memory
Current write position
: Receive data
Buffer A
Buffer B
Memory
Rev. 0, 07/98, page 263 of 453
Receive buffer
length (BFL)