HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 161

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.2.12
Status register 3 (ST3) indicates data transmit status in bit synchronous mode, whether or not the
ADPLL is in search mode in byte or bit synchronous mode, and also indicates the CTS and DCD
line levels and the transmitter/receiver status (enable or disable). This is a read-only register.
The reset descriptions of this register's bits are as follows:
No bit of this register generates an interrupt.
Bits 5, 3, and 1 are reset by a TX reset command
Bits 2 and 0 are reset by an RX reset command
All bits are reset by a hardware reset or a channel reset command
All bits are reset in system stop mode
MSCI Status Register 3 (ST3)
Async
Byte sync
Bit sync HDLC
Read/Write
Initial value
Notes:
Sending on loop
• Bit synchronous mode
0: Transmits no MSCI data
1: Transmits MSCI data
1. Reserved. These bits always read 0.
2. Undefined
—
—
7
0
*1
—
—
6
0
Search mode
• Byte/Bit synchronous mode
0: ADPLL normal mode
1: ADPLL search mode
*1
SLOOP
R
—
5
0
*1
CTS input line status
0: CTS low level
1: CTS high level
SRCH
R
—
4
0
*1
CTS
R
X
3
*2
DCD input line status
0: DCD low level
1: DCD high level
Rev. 0, 07/98, page 145 of 453
R
DCD TXENBL R XENBL
X
2
*2
TX enable
0: Disable
1: Enable
R
1
0
RX enable
0: Disable
1: Enable
R
0
0