HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 114

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HD64570

Manufacturer Part Number
HD64570
Description
Serial Communications Adaptor
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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4.3
Two types of vectors can be selected for output from the SCA. The vector is output on data bus
lines D
1.
2.
These two types of vector output are selected by setting a bit in the interrupt control register
(ITCR). See section 4.2.3, Interrupt Control Register.
4.4
Three types of acknowledge cycles can be selected for the SCA.
1.
2.
3.
If INTA goes low when no interrupt is requested (when INT is inactive), no vector is output.
Rev. 0, 07/98, page 98 of 453
output as a fixed interrupt vector.
vector register (IMVR). The other six bits are modified according to the interrupt source. The
IMVR value is output as the interrupt vector.
is driven active (low).
active (low) INTA input (figure 4.2).
in the high-impedance state. The IVR or IMVR contents are output on the data bus at the
second active (low) INTA input (figure 4.3).
Fixed vector: An arbitrary 8-bit value can be set in the interrupt vector register (IVR) for
Modified vector: An arbitrary 2-bit value can be set in bits 7 and 6 of the interrupt modified
Non-acknowledge cycle: The data bus remains in the high-impedance state even when INTA
Single acknowledge cycle: The IVR or IMVR contents are output on the data bus at the first
Double acknowledge cycle: The first active (low) INTA input is ignored; the data bus is left
7
to D
Vector Output
Acknowledge Cycle
0
. (The output on lines D
15
to D
8
is undetermined.)

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