HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 309

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Table 6.9 shows another example of MSCI-to-memory multi-frame transfer using four descriptors
and four buffers. In this example, to rewrite a buffer, the received data stored in the buffer is
moved to another area during reception operations, and EDA is updated. Steps 1 to 7 are the same
as those in table 6.8. Since the DMAC remains enabled after one frame has been transferred in
multi-frame transfer mode, some frame end interrupts (DMIB) might remain unprocessed. The
number of unprocessed interrupts is stored in the frame end interrupt counter (FCT). When the
FCT value is 1111 and frame transfer continues, a counter overflow error occurs, and the DMAC
terminates data transfer after transmitting the current frame. The FCT value is then reset to 0000,
and DMIA interrupt is generated (if enabled). For details, see sections 6.2.8, DMA Mode Register
(DMR), and 6.2.9, Frame End Interrupt Counter (FCT).
Table 6.9
Step
1
2
3
4
5
6
7
8
9
10
A
CDA: Current descriptor address register
EDA: Error descriptor address register
DE bit: Bit 1 of the DMA status register (DSR)
n
: Start address of each descriptor
DMAC
Operation
—
Writes data to
buffer 1
A
Writes data to
buffer 2
A
Writes data to
buffer 3
A
—
—
Writes data to
buffer 0
2
3
0
‡ CDA
‡ CDA
‡ CDA
MSCI-to-Memory Chained-Block Multi-Frame Transfer Mode (part of a buffer
released during reception operation )
MPU
Operation
A
A
1 ‡ DE bit
—
A
—
—
—
—
Transfers
data from
buffers 1 and
2 to another
area
A
—
1
0
1
3
‡ CDA
‡ EDA
‡ EDA
‡ EDA
CDA
Value
A
A
A
A
A
A
A
A
A
A
1
1
2
2
3
3
0
0
0
0
EDA
Value
A
A
A
A
A
A
A
A
A
A
0
0
1
1
1
1
1
1
3
3
DE Bit
Value
1
1
1
1
1
1
1
1
1
1
Note
Specifies the buffer where the
receive data is to be written using
the CDA (figure 6.21)
Writes A
maximum buffer size
After transferring receive data to
another area, the MPU rewrites
EDA to release the buffer
(figure 6.21)
Rev. 0, 07/98, page 293 of 453
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to EDA to reserve the