HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 289

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

In chained-block transfer mode, since the DMAC transfers data in frame units, different frame
data cannot be saved in the same buffer. If a buffer contains the end of a frame, the EOM bit of
the status field (ST) of the descriptor specifying the buffer must be set to 1. In single-frame
transfer mode, the DMAC terminates DMA transfer after transferring the end of the frame in the
buffer and updating the CDA value. The descriptor, with the EOT bit of ST set to 1, notifies the
DMAC of the completion of data transfer after data is transferred from the specified buffer. This
notification indicates the completion of multi-frame transfer.
At completion of frame or DMA transfer, the DMAC issues interrupt DMIB (if enabled).
EDA must initially contain the low-order 16 bits of the address of the descriptor indicating the first
buffer which contains no transmit data. In this case, if data has been written to the buffer specified
by the descriptor, the MPU can update the EDA value to indicate the start address of the descriptor
indicating the next empty buffer. (EDA can be written even while DMA is enabled.) This allows
transmit data to be added and modified while DMA is enabled.
When the CDA and EDA values are equal and a transfer request is issued, the DMAC terminates
data transfer and issues interrupt DMIA (if enabled).
Rev. 0, 07/98, page 273 of 453