HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 368

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Table 10.12 MSCI Timing (cont)
Item
ADPLL operating clock high-level
pulse width
ADPLL operating clock low-level
pulse width
CLK BRG output delay time *
TXC/RXC output rise time
TXC/RXC output fall time
RXC SYNC set-up time
RXC SYNC hold time
CTS high-level pulse width
CTS low-level pulse width
DCD high-level pulse width
DCD low-level pulse width
CLK RTS delay time
Notes: 1. In asynchronous mode and loop mode t
Table 10.13 Rise and Fall Times of Input Signals with No Characteristics Specified
(V
Item
Input signal rise time
Input signal fall time
Rev. 0, 07/98, page 352 of 453
CC
= 5 V
2. f
3. Maximum cycle time corresponds to 50 bits/s.
(CLK) frequency.)
BRG
10%, V
f
CLK
(f
SS
BRG
= 0 V, Ta = 20 to +75 C unless otherwise specified)
is the baud rate generator output frequency; f
2
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
t
t
PLHW
PLLW
BGD
BGr
BGf
SYSU
SYHD
CTSHW
CTSLW
DCDHW
DCDLW
RTSD
Ir
If
Min
10
10
2.5
2.5
2.0
2.0
2.0
2.0
Min
TCYC
and t
Typ
Typ
RCYC
= 2.5 t
Max
95
30
30
70
Max
100
100
CYC
CLK
(min).
is the system clock
Unit
ns
ns
ns
ns
ns
t
t
t
t
t
t
ns
Unit
ns
ns
CYC
CYC
CYC
CYC
CYC
CYC
Timing
Figure 10.14,
figure 10.22
Timing
Figure 10.23