HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 343

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

9.1
9.1.1
Transfer of Transmit Data: Three different types of data transfer are described below.
Transfer of Receive Data: Three different types of data transfer are described below.
9.1.2
Initialization: An example of an initialization program is given below.
Polling
The MPU determines data write timing to the transmit buffer by monitoring the TXRDY bit of
status register 0 (ST0). In this case, the TXRDY interrupt must be disabled.
Interrupt
The MPU writes data to the transmit buffer when receiving a TXRDY interrupt. The TXRDY
interrupt is issued when the TXRDYE bit of interrupt enable register 0 (IE0) is set to 1 in TX
ready state (specified by TX ready control registers 0 and 1 (TRC0 and TRC1)). In this case,
the on-chip DMAC must be disabled for transfer requests.
DMA transfer
The on-chip DMAC controls data write operation to the transmit buffer using the DMA
transfer request signal. This signal is issued when the TXRDY bit is set to 1. In this case,
TRC0 must be set to a large enough value to prevent underrun errors, and the TXRDY
interrupt must be disabled.
Polling
The MPU determines data read timing from the receive buffer by monitoring the RXRDY bit
of ST0. In this case, the RXRDY interrupt must be disabled.
Interrupt
The MPU reads data from the receive buffer when receiving an RXRDY interrupt. The
RXRDY interrupt is enabled when the RXRDYE bit of IE0 is set to 1 in RX ready state
(specified by RX ready control register (RRC)). In this case, the on-chip DMAC must be
disabled for transfer requests.
DMA transfer
The on-chip DMAC controls data read operations from the receive buffer using the DMA
transfer request signal. This signal is issued when the RXRDY bit is set to 1. In this case, the
RXRDY interrupt must be disabled.
Application Examples
Serial Data Transfer by MPU and DMAC
Transmission by Programmed I/O (Bi-Sync Mode)
Section 9 Application Examples
Rev. 0, 07/98, page 327 of 453