HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 439

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Register
MSCI (Channel 1)
MSCI Control Register
Channel 1: CTL Channel 1
MSCI Synchronous/
Address Register 0
Channel 1: SA0 Channel 1
CPU
Mode
0, 1
51H
52H
Address
CPU
Mode
2, 3
50H
53H
• Byte synchronous mode
• Bit synchronous mode
Underrun state control
• Byte synchronous mode
0:
1:
• Bit synchronous mode
0:
1:
Remarks
Mono-sync
Bi-sync
External-sync
HDLC
mode
Async
Byte sync
Bit sync HDLC
Read/Write
Initial value
Async
Byte sync
Bit sync HDLC
Read/Write
Initial/value
Enters idle state immediately
Enters idle state after CRC transmission
Enters idle state after aborting transmission
Enters idle state after FCS and flag transmission
No address field checked
Single address 1
Single address 2
Dual address
Idle state control
• Byte/Bit synchronous mode
0:
1:
Transmits a mark
Transmits an idle pattern
SYN pattern for reception
SYN pattern for transmission and reception (bit7–bit0)
Not used
SA07
R/W
—
—
7
0
—
7
1
SYN pattern for reception/address field check
R/W
SA06 SA05 SA04 SA03 SA02 SA01 SA00
—
—
6
0
—
6
1
UDRNC
R/W
R/W
—
5
0
—
5
1
Rev. 0, 07/98, page 423 of 453
Send break
•
0:
1:
Not used
Bit7–bit0 of the secondary station address
Not used
Bit7–bit0 of the secondary station address
Asynchronous
mode
Off
On (break send)
R/W
IDLC
R/W
—
4
0
—
4
1
R/W
BRK
R/W
—
3
0
—
3
1
SYN character
load enable
• Byte synchronous mode
0:
1:
SYNCLD
Disable
Enable
R/W
R/W
—
—
2
0
—
2
1
R/W
Request to send
0:
1:
R/W
—
1
0
—
1
1
Sets RTS low
Sets RTS high
R/W
RTS
R/W
0
1
—
0
1