HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 305

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

The functions of the registers used in MSCI-to-memory chained-block transfer mode are shown in
table 6.7. As can be seen from the table, in MSCI-to-memory chained-block transfer mode, either
single-frame transfer or multi-frame transfer can be selected. In single-frame transfer mode,
transfer is completed within one frame, after which the DMAC enters initial state. Here, the DE
bit of DSR is automatically cleared. When the DE bit is set to 1 again, the DMAC restarts
operation. In multi-frame transfer mode, the DMAC subsequently transfers frames of data if a
request is issued from the MSCI. When the CDA and EDA values match, the DMAC terminates
data transfer, even if an additional transfer request has been issued.
Table 6.7
Item
Number of
bits
Function
Role in
DMAC
operation
Register
update
Chain Pointer Base
(CPB)
8
Specifies the high-order
8 bits of the 24-bit descriptor
start address.
—
Under MPU control.
Control Registers Used in MSCI-to-Memory Chained-Block Transfer Mode
(reception)
Error Descriptor
Address Register (EDA)
16
Indicates the low-order
16 bits of the start address
of the descriptor following
the descriptor indicating the
last write-enabled buffer.
—
Transfer ends when a transfer request is issued while
the EDA and CDA match. An interrupt, if enabled, is
generated.
Under MPU control.
Rev. 0, 07/98, page 289 of 453
Current Descriptor
Address Register (CDA)
16
Specifies the low-order
16 bits of the start
address of the descriptor
corresponding to the first
receive buffer. This
address is updated by the
DMAC during buffer
chaining.
When the DMAC begins
receive operation,
indicates the low-order
16 bits of the start
address of the descriptor
corresponding to the
buffer being written.
When the current buffer
write is completed, the
next descriptor start
address is automatically
loaded into this register.