HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 229

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HD64570

Manufacturer Part Number
HD64570
Description
Serial Communications Adaptor
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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ADPLL automatically compensates it to within 1 operating clock cycle until the clock phase and
receive data phase are synchronized.
ADPLL specifications are shown in table 5.16. The transmission codes supported by the ADPLL
are summarized in figure 1.8.
Table 5.16 ADPLL Specifications
No. Item
1
2
3
4
Maximum
operating clock
frequency
Maximum bit
rate
Maximum
number of level
transitions
necessary for
synchronization
Receive
data noise
suppression
Mode
All
Operating
mode
Code type NRZ
Noise suppression
Operating
mode
FM
Normal
mode
Search
mode
On
8
16 1.1 Mbps
32 0.5 Mbps
8
16 8
32 16
8
16 8
32 16
8
16 x<2/16
32 x<4/32
Specification
17.6 MHz
2.2 Mbps
4
4
1
Undefined Off
x<1/8
Rev. 0, 07/98, page 213 of 453
1/8 x<2/8
2/16 x<3/16 3/16 x
4/32 x<5/32 5/32 x
2/8 x
Remarks
Sampling
ratio must
also be set

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