HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 290

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

The functions of the registers used in memory-to-MSCI chained-block transfer mode are listed in
table 6.4. As can be seen from the table, in memory-to-MSCI chained-block transfer mode, either
a single-frame transfer or multi-frame transfer can be selected. In single-frame transfer mode,
Rev. 0, 07/98, page 274 of 453
Figure 6.14 Operation Flow in Memory-to-MSCI Chained-Block Transfer Mode
No
No
Transfer one byte or one
Load the next descriptor
start address from work
word, decrement BCR,
DMAC work register
and increment BAR
Load chain pointer
Load buffer pointer
(8 bits) into DMAC
(CP) (16 bits) into
Load status (ST)
(BP) (24 bits) into
(DL) (16 bits) into
Load data length
register to CDA
work register
CDA = EDA?
(DE bit = 0)
Transfer
completed?
BCR = 0?
Yes
Yes
Start
BAR
BCR
End
No
Yes
CDA:
EDA:
BAR:
BCR:
DE bit:
Current descriptor address
register
Error descriptor address
register
Buffer address register
Byte count register
DMA status register (DSR) bit 1