HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 264

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 7 (EOT: End of Transfer): A 1 indicates that the transfer operation by the DMAC has been
completed normally, in either single-block transfer or chained-block transfer mode. See section
6.4.1, Overview, for the conditions governing DMA normal completion.
This bit is cleared when a 1 is written to the bit position.
When this bit and the EOTE bit of the DMAC interrupt enable register (DIR) are both 1, the
DMAC generates an interrupt request (DMIB). For details, see section 6.2.10, DMA Interrupt
Enable Register (DIR).
Rev. 0, 07/98, page 248 of 453
Notes: 1.
End of transfer
0:
1:
Single-block
transfer mode
Chained-block
transfer mode
Read/Write
Initial value
Transfer not completed
Transfer completed
2.
3.
Reserved. When read, these bits are undefined. They can be set to 0 or 1.
Reserved. These bits always read 0 and must be set to 0.
These bits can be cleared when a 1 is written to the bit positions.
EOT
R/W
7
0
End of frame transfer
•
0:
1:
*3
Chained-block transfer
Frame transfer not completed
Frame transfer completed
EOM
R/W
—
6
0
*1
*3
Buffer overflow/underflow
•
0:
1:
BOF
R/W
—
Chained-block transfer
No error detected
Error detected
5
0
*1
*3
Counter overflow
•
0:
1:
Chained-block
transfer
No error detected
Error detected
COF
R/W
—
0
4
*1
*3
—
—
3
0
*2
—
—
2
0
*2
DMA enable
0:
1:
Disable
Enable
R/W
DE bit write enable
0:
1:
DE
1
0
Enable
Disable
DWE
W
0
1