HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 13

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.3
5.4
5.5
5.6
5.7
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.2.10 MSCI Status Register 1 (ST1).............................................................................. 136
5.2.11 MSCI Status Register 2 (ST2).............................................................................. 139
5.2.12 MSCI Status Register 3 (ST3).............................................................................. 145
5.2.13 MSCI Frame Status Register (FST) ..................................................................... 147
5.2.14 MSCI Interrupt Enable Register 0 (IE0) .............................................................. 149
5.2.15 MSCI Interrupt Enable Register 1 (IE1) .............................................................. 151
5.2.16 MSCI Interrupt Enable Register 2 (IE2) .............................................................. 154
5.2.17 MSCI Frame Interrupt Enable Register (FIE)...................................................... 157
5.2.18 MSCI Synchronous/Address Register 0 (SA0) .................................................... 158
5.2.19 MSCI Synchronous/Address Register 1 (SA1) .................................................... 160
5.2.20 MSCI Idle Pattern Register (IDL) ......................................................................... 162
5.2.21 MSCI TX/RX Buffer Register (TRB: TRBH, TRBL) ......................................... 163
5.2.22 MSCI RX Ready Control Register (RRC) ........................................................... 168
5.2.23 MSCI TX Ready Control Register 0 (TRC0)....................................................... 169
5.2.24 MSCI TX Ready Control Register 1 (TRC1)....................................................... 170
5.2.25 MSCI Current Status Register 0 (CST0).............................................................. 171
5.2.26 MSCI Current Status Register 1 (CST1).............................................................. 172
Operation ........................................................................................................................... 174
5.3.1
5.3.2
5.3.3
Transmit/Receive Clock Sources ...................................................................................... 206
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
ADPLL .............................................................................................................................. 211
5.5.1
5.5.2
5.5.3
Baud Rate Generator.......................................................................................................... 225
5.6.1
5.6.2
5.6.3
Interrupts............................................................................................................................ 234
5.7.1
5.7.2
MSCI RX Clock Source Register (RXS) ............................................................. 121
MSCI TX Clock Source Register (TXS).............................................................. 123
MSCI Time Constant Register (TMC) ................................................................. 125
MSCI Command Register (CMD)........................................................................ 126
MSCI Status Register 0 (ST0).............................................................................. 131
Asynchronous Mode ............................................................................................ 174
Byte Synchronous Mode ...................................................................................... 190
Bit Synchronous Mode ......................................................................................... 197
Overview .............................................................................................................. 206
Transmit Clock Sources ....................................................................................... 208
Receive Clock Sources ......................................................................................... 209
Baud Rate Generator ............................................................................................ 210
ADPLL ................................................................................................................. 210
Overview .............................................................................................................. 211
Operation .............................................................................................................. 214
Notes on Usage..................................................................................................... 220
Overview .............................................................................................................. 225
Functions .............................................................................................................. 226
Register Set Values and Bit Rates........................................................................ 227
Interrupt Types and Sources................................................................................. 234
Interrupt Clear ...................................................................................................... 234
Rev. 0, 07/98, page iii of 11