HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 283

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

6.4.2
Operation: The HD64570 allows single-block transfers (single address) from the MSCI to
memory via DMAC channels 0 and 2, and from memory to the MSCI via DMAC channels 1 and
3.
In MSCI-to-memory single-block transfer mode, the destination start address and transfer byte
count must be set in the destination address register (DAR) and byte count register (BCR),
respectively, in DMAC channels 0 and 2. Similarly, in memory-to-MSCI single-block transfer
mode, the source start address and transfer byte count must be set in the source address register
(SAR) and BCR, respectively, in the DMAC channels 1 and 3.
Single-block transfer between memory and the MSCI is shown in figure 6.10. As shown in the
figure, in MSCI-to-memory transfer mode, as many bytes of data as specified by BCR are DMA-
transferred in byte units from the MSCI receiver to the memory address specified by DAR of
channels 0 and 2. Similarly, in memory-to-MSCI transfer mode, as many bytes of data as
specified by BCR are DMA-transferred in byte units from the memory address specified by SAR
of channels 1 and 3 to the MSCI transmitter.
During transfer, the BCR value is decremented by 1 each time the DMAC has transferred one byte
of data, and is decremented by 2 each time the DMAC has transferred one word of data. When the
BCR value reaches 0000H, the DMAC terminates data transfer and enters initial state. At this
time, the DMAC generates an interrupt (if enabled). Note that when the BCR value reaches
0001H, the DMAC transfers one byte of data instead of one word of data, decrementing the BCR
value to 0000H.
DMA control register
channels 0, 2
DMA control register
channels 1, 3
Memory-to/from-MSCI Single-Block Transfer Mode
Figure 6.10 Memory-to/from-MSCI Single-Block Transfer Mode
BCR (16 bits)
BCR (16 bits)
DAR (24 bits)
SAR (24 bits)
HD64570
Destination
start address
Transmit/receive memory area
Rev. 0, 07/98, page 267 of 453