HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 50

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

1.7.11
Figure 1.22 shows the structure of a descriptor. Descriptors are allocated in memory in different
ways, depending on the CPU mode.
Note:
Rev. 0, 07/98, page 34 of 453
Address
2n + 9
2n + 7
2n + 5
2n + 3
2n + 1
Address
2n + 8
2n + 6
2n + 4
2n + 2
2n
Reserved fields in descriptors are not written by the DMAC, but retain their previous
values. The MPU may write in these fields, but this does not affect the DMAC.
Descriptors must start at an even address (2n). Correct operation is not assured if a
descriptor starts at an odd address.
Descriptor Structure
Bit 15
Bit 15
Buffer pointer H (BPH)
Chain pointer H (CPH)
Buffer pointer H (BPH)
Chain pointer H (CPH)
Data length H (DLH)
Data length H (DLH)
Address
2n + 9
2n + 8
2n + 7
2n + 6
2n + 5
2n + 4
2n + 3
2n + 2
2n + 1
2n
Reserved
Reserved
Reserved
Reserved
Figure 1.22 Descriptor Structure
Bit 7
1. CPU Mode 1
2. CPU Mode 0
3. CPU Modes 2, 3
Buffer pointer H (BPH) 8 bits
Chain pointer H (CPH) 8 bits
Buffer pointer B (BPB) 8 bits
Buffer pointer L (BPL) 8 bits
Chain pointer L (CPL) 8 bits
Data length H (DLH) 8 bits
(Note)
(Note)
Data length L (DLL) 8 bits
(Note)
(Note)
Status (ST) 8 bits
Bit 8
Bit 8
Reserved
Reserved
Bit 7
Bit 7
Buffer pointer B (BPB)
Buffer pointer B (BPB)
Buffer pointer L (BPL)
Chain pointer L (CPL)
Buffer pointer L (BPL)
Chain pointer L (CPL)
(Note)
(Note)
Data length L (DLL)
Data length L (DLL)
Status (ST)
Status (ST)
Bit 0
Bit 0
Bit 0
Address
2n + 8
2n + 6
2n + 4
2n + 2
2n
Address
2n + 9
2n + 7
2n + 5
2n + 3
2n + 1