HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 233

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

T
T
T
T
T
ADPLL operating clock
(operating mode: x 8)
Receive data
Extracted clock
Receive data
syncronized with the
extracted clock
B
C
D
S-1
S
:
:
:
:
and T
ADPLL detects no level transition in FM-code receive data in the successive two bit
cycles, or "windows" (from the bit boundary to 1/4 T
and the CLMD bit of MSCI status register 1 (ST1) is set to 1.
Figure 5.34 NRZ Receive Data Phase Compensation in Operating Mode
S-2
: Receive data level transitions after noise suppression
One receive data bit time
One ADPLL operating clock cycle
Delay time between the receive data input to the ADPLL and the receive data after
passing the noise suppressor and data delay unit
Synchronized transitions of noise-suppressed receive data after noise suppression.
T
D
T
B
T
T
S-2
C
T
S-1
B
or from 3/4 T
Rev. 0, 07/98, page 217 of 453
B
T
S
to the bit boundary),
T /2
B
T /2
8
B
T
S