HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 293

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Table 6.5
Step
1
2
3
4
5
6
7
8
A
CDA: Current descriptor address register
EDA: Error descriptor address register
DE bit: Bit 1 of the DMA status register (DSR)
n
:
DMAC
Operation
—
Reads data
from buffer 0
A
Reads data
from buffer 1
A
0 ‡ DE bit
—
Reads data
from buffer 2
A
0 ‡ DE bit
Start address of each descriptor
1
2
3
‡ CDA
‡ CDA
‡ CDA
Memory-to-MSCI Chained-Block Single-Frame Transfer Mode (no transmit
data added during transmission)
MPU
Operation
A
A
1 ‡ DE bit
—
—
—
—
1 ‡ DE bit
—
—
0
3
‡ CDA
‡ EDA
CDA
Value
A
A
A
A
A
A
A
A
0
0
1
1
2
2
2
3
EDA
Value
A
A
A
A
A
A
A
A
3
3
3
3
3
3
3
3
DE Bit
Value
1
1
1
1
0
1
1
0
Note
Specifies the first buffer containing
data to be transmitted using CDA,
and specifies the next to last buffer
using EDA. (see figure 6.15.)
Clears the DE bit after the transfer
of one frame. When a 1 is written
to the DE bit, the DMAC can
accept a transfer request.
When a 1 is written to the DE bit,
and a transfer request is issued,
the DMAC generates a DMIA
interrupt. (see figure 6.15.)
Rev. 0, 07/98, page 277 of 453