HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 269

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bits 7–4: Reserved. These bits always read 0.
Bits 3–0 (FCT3–FCT0: Frame End Interrupt Counter Value): The function of these bits is
described below.
FCT is enabled or disabled by the CNTE bit of DMA mode register (DMR). For details, see
section 6.2.8, DMA Mode Register (DMR).
The EOM bit of the DMA status register (DSR) remains 1 when the FCT value is not 0000. When
a 1 is written to the EOM bit, the FCT value is decremented. (While FCT is enabled and its value
is 0000, the EOM bit of DSR must not be set to 1.) If frame transfer continues after the FCT value
reaches 1111, the DMAC terminates transfer operation when the next frame transfer has been
completed. At this time, the COF bit of DSR is set to 1. If the COFE bit of the DMA interrupt
enable register (DIR) is 1, the DMAC generates a counter overflow interrupt (DMIA). Here, the
FCT value reaches 0000, and the EOM bit is set to 1. The EOM bit can be cleared by a frame end
interrupt counter clear command specified by the DMA command register (DCR). For
commands, see section 6.2.11, DMA Command Register (DCR).
Single-block transfer mode
Reserved. When read, the value of these bits is undefined.
Chained-block transfer mode
In multi-frame chained-block transfer mode, the DMAC can request a DMIB interrupt (frame
end interrupt) at completion of each frame. (The DMAC remains enabled and successive
interrupts can occur.) If the transfer of successive requested frames is completed before the
MPU executes the interrupt processing routine, some interrupt requests might remain
unprocessed. The frame interrupt counter (FCT) counts such interrupts.
Notes: 1.
Single-block
transfer mode
Chained-block
transfer mode
Read/Write
Initial value
2.
Reserved. These bits always read 0.
Reserved. When read, these bits are undefined.
—
—
7
0
*1
—
—
6
0
*1
—
—
5
0
*1
—
—
4
0
Frame end interrupt counter (FCT) value
*1
FCT3
—
R
3
0
*2
FCT2
—
Rev. 0, 07/98, page 253 of 453
R
2
0
*2
FCT1
—
R
1
0
*2
FCT0
—
R
0
0
*2