HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 163

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 0 (RXENBL: RX Enable): Indicates whether the receiver is enabled or disabled. Receiver
enable/disable selection is performed by a command. This is a read-only bit, and writing to it has
no effect.
5.2.13
The frame status register (FST) (figure 5.16) holds the status of the last frame received in bit
synchronous mode.
The reset descriptions of this register's bits are as follows:
When the EOMF bit is set to 1, an MPU interrupt request is generated (if enabled). The other bits
do not generate interrupts.
When data with EOM bit = 1 (last character of the frame) is read from the receive buffer, the
character status, which is reflected by bits 7 2 of status register 2 (ST2), is transferred and set in
FST. This clears all bits of ST2 (figure 5.5). The definition of each bit of FST is the same as that
of the corresponding bit of ST2. See section 5.2.11, MSCI Status Register 2 (ST2).
TXENBL = 1:Indicates that the transmitter is enabled
Asynchronous/Byte synchronous/Bit synchronous mode
RXENBL = 0:
RXENBL = 1:
When 1 is written to a particular bit position, that bit is reset
All bits are reset by an RX or channel reset command
All bits are reset in system stop mode
MSCI Frame Status Register (FST)
Async
Byte sync
Bit sync HDLC
Read/Write
Initial value
Note: The bits marked with * are reserved. These bits always read 0 and can be
set to 0 or 1.
EOMF SHRTF ABTF RBITF OVRNFCRCEF
R/W
Indicates that the receiver is disabled
Indicates that the receiver is enabled
—
7
0
*
Frame status at receive completion
R/W
—
6
0
*
R/W
—
5
0
*
R/W
—
4
0
*
R/W
—
3
0
*
Rev. 0, 07/98, page 147 of 453
R/W
—
2
0
*
—
—
1
0
*
—
—
0
0
*