HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 167

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.2.15
Interrupt enable register 1 (IE1) enables or disables interrupt requests when the status bits of status
register 1 (ST1) are set to 1. For details on interrupts, see section 5.7, Interrupts.
UDRN interrupt enable
• Byte/Bit synchronous mode
0: Disable
1: Enable
Note: The bits marked with * are reserved. These bits always
Async
Byte sync
Bit sync
HDLC
Read/Write
Initial value
MSCI Interrupt Enable Register 1 (IE1)
IDL interrupt enable
0: Disable
1: Enable
read 0 and must be set to 0.
CLMD interrupt enable
• Byte/Bit synchronous mode
0: Disable
1: Enable
UDRNE
R/W
—
7
0
*
SYNCD interrupt enable
• Byte synchronous mode
0: Disable
1: Enable
FLGD interrupt enable
• Bit synchronous mode
0: Disable
1: Enable
R/W
IDLE
6
0
CLMDE
R/W
—
5
0
*
CCTS interrupt
enable
0: Disable
1: Enable
SYNCDE
FLGDE
R/W
—
4
0
*
CCTSE
CDCD interrupt enable
0: Disable
1: Enable
R/W
3
0
CDCDE
R/W
2
0
BRKD interrupt enable
• Asynchronous mode
0: Disable
1: Enable
Rev. 0, 07/98, page 151 of 453
ABTD interrupt
enable
• Bit sychronous mode
0: Disable
1: Enable
BRKDE
ABTDE
R/W
—
1
0
*
IDLD interrupt enable
• Bit synchronous mode
0: Disable
1: Enable
BRKE interruput enable
• Asynchronous mode
0: Disable
1: Enable
BRKEE
IDLDE
R/W
—
0
0
*