HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 82

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

an input in SCA slave mode and is an output in master mode.) When the SCA detects BUSACK
low and if no other bus master is using the bus, that is, BUSY is high, the SCA acquires control of
the bus. Having acquired control of the bus, the SCA drives BUSY (output) low at the next rising
edge of CLK to indicate that it has received control of the bus. The SCA begins a DMA cycle at
the next rising edge of CLK.
When a DMA transfer request has been serviced, the SCA releases control of the bus. Specifically,
the SCA drives BUSREQ inactive, which terminates the DMA cycle at the next falling edge of
CLK. At the same falling edge of CLK, the SCA drives BUSY inactive to indicate that the SCA
has released control of the bus. (Since the BUSY line is an open-drain output, it must be pulled up
to V
.)
CC
Figure 3.6 (b) shows the bus arbitration sequence in which a DMA transfer is requested in the
SCA while the master MPU does not have control of the bus.
In this case, since BUSACK is low, the SCA only samples the BUSY input at each rising edge of
CLK. When the SCA detects BUSY high, that is, no other bus master is using the bus, the SCA
immediately drives BUSY (output) low to indicate that the SCA has received control of the bus.
The SCA then drives BUSREQ active at the next falling edge of CLK and drives BEO inactive
(high) to stop BUSACK from being transferred to the lower bus masters. The SCA begins a DMA
cycle at the next rising edge of CLK.
The bus release sequence is similar to that in figure 3.6 (a).
When the master MPU later drives BUSACK high, BEO goes high at the next rising edge of CLK.
Figure 3.6 (c) shows the bus arbitration sequence in which the SCA requests control of the bus
while another bus master is using it, and the SCA acquires control of the bus after the bus master
releases control of the bus with the BUSACK input from the master MPU kept low.
Rev. 0, 07/98, page 66 of 453