HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 307

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Table 6.8
Step
1
2
3
4
5
8
9
A
CDA: Current descriptor address register
EDA: Error descriptor address register
DE bit: Bit 1 of the DMA status register (DSR)
n
:
DMAC
Operation
—
Writes data to
buffer 2
A
Writes data to
buffer 3
A
Writes data to
buffer 1
A
Start address of each descriptor
3
0
2
‡ CDA
‡ CDA
‡ CDA
MSCI-to-Memory Chained-Block Multi-Frame Transfer Mode (normal
reception operation)
MPU
Operation
A
A
1 ‡ DE bit
—
A2 ‡ EDA
—
—
—
—
2
1
‡ CDA
‡ EDA
CDA
Value
A
A
A
A
A
A
A
2
2
3
3
0
1
2
EDA
Value
A
A
A
A
A
A
A
1
1
2
2
2
2
2
DE Bit
Value
1
1
1
1
1
1
1
Note
Specifies the buffer where
receive data is to be written using
CDA and EDA (figure 6.20)
Writes A
maximum buffer size
If another write request is issued in
this state, the DMAC generates a
DMIA interrupt (figure 6.20)
Rev. 0, 07/98, page 291 of 453
2
to EDA to reserve the