HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 152

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.2.10
Status register 1 (ST1) indicates status information such as break start/stop detection in
asynchronous mode, underrun error, and SYN pattern detection in byte synchronous mode,
underrun error, flag, abort, DPLL error, and idle start detection in bit synchronous mode, and also
indicates transmitter idle status, and CTS and DCD input level changes in all modes.
The reset descriptions of this register's bits are as follows:
When any bit of this register is set to 1, an MPU interrupt request is generated (if enabled).
Rev. 0, 07/98, page 136 of 453
Underrun error
•
0:
1:
Byte/Bit synchronous
mode
No underrun detected
Underrun detected
Bits 7, 4, 3, 2, 1, and 0 are reset when 1 is written to the corresponding bit.
Bits 7, 6, and 3 are reset by a TX reset command.
Bit 6 is reset when data is written to the transmit buffer.
Bits 4, 2, 1, and 0 are reset by an RX reset command.
All bits are reset by a channel reset command or in system stop mode.
Notes:
Async
Byte sync
Bit sync
HDLC
Read/Write
Initial value
MSCI Status Register 1 (ST1)
1. Reserved. These bits always read 0 and can be set to 0 or 1.
2. Reserved. When read, this bit is undefined and must be set to 0.
Transmitter idle status
0: Not idle
1: Idle
UDRN
R/W
—
7
0
Two-clock missing detection
• Byte/Bit synchronous mode
0: Two missing clock transitions not detected
1: Two missing clock transitions detected
*1
IDL
SYN pattern detection
• Byte synchronous mode
0: No pattern detected
1: Pattern detected
Flag detection
• Bit synchronous mode
0: No flag detected
1: Flag detected
R
6
0
CLMD
R/W
—
5
0
*2
SYNCD
FLGD
R/W
—
4
0
*1
CTS line
level change
0: Not changed
1: Changed
CCTS
R/W
3
0
DCD line
level change
0: Not changed
1: Changed
CDCD
R/W
2
0
BRKD
ABTD
R/W
Abort detection
• Bit synchronous mode
0: Abort sequence start not detected
1: Abort sequence start detected
Break detection
• Asynchronous mode
0: Break sequence starts not detected
1: Break sequence starts detected
—
1
0
*1
Break end
• Asynchronous mode
0: Break sequence end not detected
1: Break sequence end detected
Idle start detection
• Bit synchronous mode
0: Idle sequence start not detected
1: Idle sequence start detected
BRKE
R/W
IDLD
—
0
0
*1