HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 211

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Error Checking: Involves the following items.
CRC error and CRC code transmission
The MSCI supports two CRC code types: CRC-16 and CRC-CCITT. The program can select
the type to be used and the initial value (all 0s or 1s) with the CRC1 CRC0 bits of MD0.
16
15
2
16
12
5
The CRC polynomial is X
+ X
+ X
+ 1 for CRC-16, and X
+ X
+ X
+ 1 for CRC-
CCITT.
The transmitter and receiver both have a CRC calculator.
The TX CRC calculator is automatically initialized immediately before data field transmission.
It can also be initialized when a TX CRC initialization command is issued.
During transmission, SYN characters are excluded from the CRC calculation. Specific data
can also be excluded (in character units) from the CRC calculation by a TX CRC calculation
exclusion command. Use the CRCCC bit of MD0 and the end of message command to enable
CRC code transmission. The CRC code is transmitted automatically when both the CRCCC
bit and the UDRNC bit of CTL are set to 1 in underrun state. If an underrun error occurs while
UDRNC or CRCCC is 0, the MSCI directly enters idle state without transmitting the CRC
code. For details, see section 5.2.1, MSCI Mode Register 0 (MD0), section 5.2.4, MSCI
Control Register (CTL), and section 5.2.8, MSCI Command Register (CMD).
The RX CRC calculator is automatically initialized immediately before data field reception. It
can also be initialized when an RX CRC initialization command is issued.
During reception, the characters not to be input to the receive buffer, such as SYN characters,
are excluded from the CRC calculation. Specific data can be also excluded (by character) from
the CRC calculation by an RX CRC calculation exclusion command. The CRC code check is
completed 15 system clock cycles after the character following the last checked character has
entered the receive buffer. If a CRC calculation forcing command is issued and if the character
following the last character does not enter the receive buffer, the check is completed 15 system
clock cycles after the command has been issued. In either case, the CRC error status is valid
until the next character enters the receive buffer.
When a CRC error is detected, the CRCE bit of status register 2 (ST2) is set to 1. This
generates an interrupt request (if enabled). For details, see section 5.2.11, MSCI Status
Register 2 (ST2).
Overrun error
An overrun error occurs when the receive buffer is full when new data is transferred.
When an overrun error occurs, the new data overwrites the top stage of the receive buffer,
erasing the previous data. At the same time, the top stage of the status FIFO is overwritten
with the status (indicating an overrun) of the new data.
The OVRN bit of ST2 is set to 1 when the new data is ready to be read. This generates an
interrupt request (if enabled).
Even if an overrun error occurs, subsequent characters are received normally. However, the
OVRN bit is not cleared even if the subsequent data causes no overrun error. It is cleared only
when a 1 is written to the bit position or ST2 is reset.
Rev. 0, 07/98, page 195 of 453