HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 182

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Table 5.9
Read Mode
Word write
Byte write
Table 5.10 TRB Write Operation in CPU Mode 1
Read Mode
Byte write
Table 5.11 TRB Write Operation in CPU Modes 2, 3
Read Mode
Word write
Byte write
Notes: 1. Because the empty data byte count in the transmit buffer is unknown to the user, extra
Rev. 0, 07/98, page 166 of 453
2. TRBH and TRBL are simultaneously accessed in word write mode, and either TRBH or
3. Empty bytes A and B are arranged in the order as shown in figures 5.9 (a) and (b). The
4. Data is lost except in built-in DMA transfer. Data in the transmit buffer is not lost, but
care must be taken in writing data to the transmit buffer using the MPU. Set the
TRC14 TRC10 bits of TX ready control register 1 (TRC1) to 1EH or less in CPU modes
0, 2, and 3 (1FH in CPU mode 1), and confirm that the TXRDY bit of status register 0
(ST0) is 1 before writing data to the transmit buffer. (Do not write data to the transmit
buffer when the TXRDY bit is 0.) However, this procedure is not necessary in built-in
DMA transfer.
TRBL is accessed in byte write mode.
transmit buffer sends A and B to the serial unit in that order.
writing data to the full buffer does not guarantee subsequent operation.
TRB Write Operation in CPU Mode 0
Accessed Register*
TRBH
TRBL
TRBH
TRBL
Accessed Register*
TRBH
TRBL
Accessed Register*
TRBH
TRBL
TRBH
TRBL
2
2
2
2 or More Bytes
B*
A*
A*
A*
2 or More Bytes
A*
A*
2 or More Bytes
A*
B*
A*
A*
3
3
3
3
3
3
3
3
3
3
Empty Data Byte Count in Transmit Buffer*
Empty Data Byte Count in Transmit Buffer*
Empty Data Byte Count in Transmit Buffer*
1 Byte
A*
A*
1 Byte
A*
A*
1 Byte
A*
A*
*
*
*
*
3
3
3
3
3
3
4
4
4
4
None
None
None
*
*
*
*
*
*
*
*
*
*
4
4
4
4
4
4
4
4
4
4
1
1
1