HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 254

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.7.3
The conditions for the TXRDY, RXRDY, TXINT, and RXINT interrupt requests are listed below.
See figure 1.25 for the relationship between interrupt requests, their status bits, and enable bits of
each register.
5.8
When the MSCI is reset, (1) the receiver and transmitter are disabled, (2) the transmit/receive
buffers are cleared, (3) the input/output lines (RXC and TXC) are set for input, (4) the output lines
(TXD and RTS) are inactivated, and (5) all the internal registers are initialized.
In addition, (1) asynchronous mode with 1 stop bit, 8-bit character length, 1/1 clock rate, and
without parity is selected; (2) full-duplex communication with NRZ code is selected; (3) the
transmit/receive status bits and interrupt enable bits are cleared; (4) the TXC line input serves as
the transmit clock and the RXC line input as the receive clock; (5) the ADPLL and baud rate
generator are initialized.
Rev. 0, 07/98, page 238 of 453
TXRDY interrupt request condition
TXRDY = TXRDY TXRDYE
RXRDY interrupt request condition
RXRDY = RXRDY RXRDYE
TXINT interrupt request condition
TXINT = TXINT TXINTE
where, TXINT = UDRN UDRNE + IDL IDLE + CCTS CCTSE
RXINT interrupt request condition
RXINT = RXINT RXINTE
where, RXINT =
+ (BRKD/ABTD) (BRKDE/ABTDE)
+ (BRKE/IDLD) (BRKEE/IDLDE) + EOM EOME
+ (PMP/SHRT) (PMPE/SHRTE) + (PE/ABT) (PEE/ABTE)
+ (FRME/RBIT) (FRMEE/RBITE) + OVRN OVRNE
+ CRCE CRCEE + EOMF EOMFE
+ CLMD CLMDE
Interrupt Enable Conditions
Reset Operation
(SYNCD/FLGD) (SYNCDE/FLGDE) + CDCD CDCDE