HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 257

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

6.2
6.2.1
One set of three 8-bit subregisters, serving as the destination address register (DAR) or buffer
address register (BAR) depending on the transfer mode, is provided for each of channels 0, 1, 2,
and 3 (figure 6.1).
Single-Block Transfer Mode: In single-block transfer mode, these subregisters serve as the
destination address register (DAR: DARL, DARH, DARB) for specifying the destination address
to which data is to be transferred. DARB, DARH, and DARL specify bits 23–16, 15– 8, and 7–0
of the 24-bit destination address, respectively. This register can directly access a maximum of 16
Mbytes of memory space.
This register must be set in DMA initial state. (The DMAC has the following operation states:
initial, enable, and halt states. For details, refer to section 6.2.11, DMA Command Register
(DCR).)
After reset, the value of this register is undefined.
Chained-Block Transfer Mode: In chained-block transfer mode, these subregisters serve as the
buffer address registers (BAR: BARL, BARH, BARB) for indicating the address of the data in the
buffer currently being accessed. BARB, BARH, and BARL specify bits 23–16, 15– 8, and 7–0 of
the 24-bit memory address currently being accessed, respectively. MPU cannot write to this
register in this mode.
After reset, the value of these registers is undefined.
Registers
Channels 0, 2: Destination Address Register (DAR: DARL, DARH,
DARB)/Buffer Address Register (BAR: BARL, BARH, BARB)
Channels 1, 3: Buffer Address Register (BAR: BARL, BARH, BARB)
Rev. 0, 07/98, page 241 of 453