HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 14

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.8
Section 6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Section 7
7.1
7.2
Rev. 0, 07/98, page iv of 11
5.7.3
Reset Operation ................................................................................................................. 237
Overview............................................................................................................................ 239
6.1.1
6.1.2
Registers ............................................................................................................................ 241
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10 DMA Interrupt Enable Register (DIR)................................................................. 254
6.2.11 DMA Command Register (DCR)......................................................................... 256
6.2.12 DMA Priority Control Register (PCR)................................................................. 258
6.2.13 DMA Master Enable Register (DMER) ............................................................... 260
Descriptors......................................................................................................................... 261
6.3.1
6.3.2
Operating Modes ............................................................................................................... 265
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
Interrupts............................................................................................................................ 300
Reset Operation ................................................................................................................. 301
Precautions ........................................................................................................................ 301
Overview............................................................................................................................ 303
7.1.1
7.1.2
Registers ............................................................................................................................ 304
Interrupt Enable Conditions ................................................................................. 237
Direct Memory Access Controller (DMAC)
Functions .............................................................................................................. 239
Configuration and Operation................................................................................ 240
Channels 0, 2: Destination Address Register (DAR: DARL, DARH, DARB)/
Buffer Address Register (BAR: BARL, BARH, BARB)
Channels 1, 3: Buffer Address Register (BAR: BARL, BARH, BARB) .......... 241
Channels 0, 2: Chain Pointer Base (CPB)
Channels 1, 3: Source Address Register (SAR: SARL, SARH, SARB)/
Chain Pointer Base (CPB).................................................................................... 242
Current Descriptor Address Register (CDA: CDAL, CDAH) ............................ 244
Error Descriptor Address Register (EDA: EDAL, EDAH) ................................ 245
Receive Buffer Length Register (BFL: BFLL, BFLH) ....................................... 246
Byte Count Register (BCR: BCRL, BCRH) ....................................................... 247
DMA Status Register (DSR) ................................................................................ 248
DMA Mode Register (DMR) ............................................................................... 251
Frame End Interrupt Counter (FCT) .................................................................... 253
Memory-to-MSCI Chained-Block Transfer Mode (Transmission) ..................... 261
MSCI-to-Memory Chained-Block Transfer Mode (Reception)........................... 263
Overview .............................................................................................................. 265
Memory-to/from-MSCI Single-Block Transfer Mode......................................... 267
Memory-to-MSCI Chained-Block Transfer Mode .............................................. 271
MSCI-to-Memory Chained-Block Transfer Mode .............................................. 285
DMAC Characteristics ......................................................................................... 299
Timer
Functions .............................................................................................................. 303
Configuration and Operation................................................................................ 303
.................................................................................................................. 303
.......................................... 239