HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 276

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

6.2.13
The DMA master enable register (DMER), shared by channels 0, 1, 2, and 3, enables or disables
DMA master operation. This register can be accessed only in byte units.
Bit 7 (DME: DMA Master Enable): Enables or disables channels 0, 1, 2, or 3 in either single-
block transfer mode or chained-block transfer mode as follows.
DME = 0: Disables all channels
DME = 1: Enables channel(s) depending on the DE bit of the DMA status register (DSR) of each
After reset, the value of the DME bit is 1.
Bits 6–0: Reserved. These bits always read 0 and must be set to 0.
Rev. 0, 07/98, page 260 of 453
DMA Master Enable Register (DMER)
Note: Bits 6–0 are reserved. These bits always read 0 and must be set to 0.
Single-block
transfer mode
Chained-block
transfer mode
Read/Write
Initial value
channel
DMA master enable
0:
1:
Disable
Enable
DME
R/W
7
1
—
—
6
0
—
5
—
0
—
—
4
0
—
—
3
0
—
—
2
0
—
—
1
0
—
—
0
0