HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 291

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

transfer is completed within one frame, after which the DMAC enters initial state. Here, the DE
bit of DSR is automatically cleared. When the DE bit is set to 1 again, the DMAC restarts
operation.
Table 6.4
Register
Name
Number of
bits
Function
Role in
DMAC
operation
Register
update
Register
updated
by the
MPU
Chain Pointer Base
(CPB)
8
Specifies the high-order
8 bits of the 24-bit descriptor
start address.
—
Under MPU control.
Initialized before
transmission.
Control Registers Used in Memory-to-MSCI Chained-Block Transfer Mode
(transmission)
Error Descriptor
Address Register (EDA)
16
Specifies the low-order
16-bits of the start address
of the descriptor corre-
sponding to the buffer
following the last transmit
buffer.
—
Transfer ends when a transfer request is issued while
the EDA and CDA match. An interrupt is generated, if
enabled.
Under MPU control.
Loaded with the start
address of the descriptor
indicating the buffer following
the last buffer containing
transmit data. To add
transmit data during a
transmission, load the start
address of the descriptor
indicating the next buffer to
be written.
Rev. 0, 07/98, page 275 of 453
Current Descriptor
Address Register (CDA)
16
Specifies the low-order
of the descriptor
corresponding to the first
transmit buffer.
This address is updated
by the DMAC during
buffer chaining.
After the DMAC starts,
it loads the low-order
16 bits of the start
address of the descriptor
corresponding to the
buffer being transferred
into the MSCI.
When the current buffer
read is completed, the
next descriptor start
address is automatically
loaded into this register.
The start address of the
descriptor indicating the
first buffer containing
transmit data is loaded
before transmission
starts.