HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 280

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

This field is controlled by the DMAC in MSCI-to-memory chained-block transfer mode. After
received data is loaded into the buffer, the DMAC loads the byte count of the data into this field.
Status (ST) (8 Bits): Indicates the status of the data in the buffer corresponding to the descriptor.
After data is loaded into the buffer, the DMAC loads the status of the data into this field.
This field is controlled by the DMAC in MSCI-to-memory chained-block transfer mode.
ST configuration for MSCI-to-memory chained-block transfer mode (reception) is shown in table
6.2.
Table 6.2
Bit
7
6
5
4
3
2
1
0
When a frame ends in the buffer corresponding to the descriptor, ST bit 7 to bit 0 are loaded with
the MSCI frame status register (FST) value, which is set immediately after the MSCI transmits the
end of frame from the receive buffer to the data bus. (For bit 7 to bit 0, see sections 5.2.11, MSCI
Status Register 2 (ST2), and 5.2.13, MSCI Frame Status Register (FST). When no frame ends in
the buffer corresponding to the descriptor and if the buffer is switched during one frame, ST bit 7
to bit 0 are cleared.
Rev. 0, 07/98, page 264 of 453
Function
EOM
Short frame
Abort
Residual bit
Overrun
CRC
Not used
Not used
Status Configuration (reception)