HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 147

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.2.9
Status register 0 (ST0) indicates the status of interrupts (TXINT and RXINT) and the
transmit/receive buffer. When any bit of this register is set to 1, an MPU interrupt request is
generated (if enabled).
This register is reset under either of the following conditions:
Hardware reset
Channel reset command
System stop mode
Notes:
Async
Byte sync
Bit sync HDLC
Read/Write
Initial value
MSCI Status Register 0 (ST0)
1. Reserved. These bits always read 0.
2. TRC14–TRC10 bits of TX ready control register 1 (TRC1)
3. TRC04–TRC00 bits of TX ready control register 0 (TRC0)
4. RRC4–RRC0 bits of RX ready control register (RRC)
5. In bit synchronous mode, RXRDY is set to 1 when data with EOM enters the
TXINT interrupt
0: No interrupt
1: Interruput
receive buffer.
TXINT
R
7
0
RXINT interrupt
0: No interrupt
1: Interruput
RXINT
R
6
0
—
—
5
0
*1
TX ready
0: Transmit buffer satisfies
1: Transmit buffer satisfies
—
—
the conditions set by TRC1
the conditions set by TRC0
4
0
*1
—
—
3
0
*1
RX ready
0: Receive buffer empty
1: Receive buffer satisfies
—
the conditions set by RRC
—
2
0
Rev. 0, 07/98, page 131 of 453
*1
TXRDY
R
1
0
*2
*3
RXRDY
R
0
0
*4, *5