HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 93

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Transfer of Three or More Bytes from Odd Address: In CPU modes 0, 2, and 3, to transfer
three or more bytes starting at an odd address by direct memory access, the DMAC first transfers
one byte from the odd address, then transfers successive words starting from the next even
address. If one byte remains to be transferred at the end, it is transferred from an even address.
Figure 3.14 shows an example of data transfer starting from an odd address.
Figures 3.15 to 3.17 show the master mode bus transfer timing sequence in each CPU mode.
2n + 7
2n + 5
2n + 3
2n + 1
D
(3)
(2)
(1)
15
Byte transfer
—
(a) CPU Mode 0
Figure 3.14 Data Transfer from Odd Address (example)
Word transfer
Word transfer
D
8
D
(4)
7
Byte transfer
—
D
0
2n + 6
2n + 4
2n + 2
2n
2n + 6
2n + 4
2n + 2
2n
D
(4)
(3)
(2)
15
Byte transfer
(b) CPU Modes 2 and 3
2n, 2n + 1,
—
Word transfer
Word transfer
Rev. 0, 07/98, page 77 of 453
D
8
D
(1)
7
are addresses
Byte transfer
—
D
0
2n + 7
2n + 5
2n + 3
2n + 1