HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 226

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.4.4
The output frequency of the baud rate generator for transmission and reception is obtained by the
following equation:
Frequencies determined by the above equation are independently output for transmission and
reception from the baud rate generator.
5.4.5
In byte or bit synchronous mode, either of two receive clocks can be used for the MSCI: a clock
extracted from the receive data by the ADPLL or the noise-suppressed RXC line input by ADPLL.
The ADPLL has the following operating modes:
operating clock rate to the bit rate). In other words, the operating clock frequency must be 8, 16,
or 32 times the bit rate, to use the ADPLL clock extraction function, regardless of the source of the
operating clock. The DRATE1 DRATE0 bits of mode register 2 (MD2) selects the ADPLL
operating mode.
Rev. 0, 07/98, page 210 of 453
CLK
RXC line
f
f
TMC:
BR:
BRG
CLK
Baud Rate Generator
ADPLL
f
:
:
BRG
baud rate
generator
Receive
=
BRG output frequency
System clock frequency
Value (1 256) set in the time constant register (TMC)
Value (0 9) set in the TXBR3 TXBR0 bits of TXS, or the RXBR3 RXBR0
bits of RXS
TMC
f
CLK
(c) Receive Clock Noise Suppression
Figure 5.31 Receive Clock Sources (cont)
f
(TMC: 1 to 256,
RXBR: 0 to 9)
BRG
Receive clock
=
f
TMC
BR
f
2
CLK
BR
÷ 2
f
CLK
RXBR
: System clock (CLK) frequency
(Sampling rate:
operating clock
8, 16, and 32 (ratio of the ADPLL
ADPLL operating clock
8, 16, 32)
ADPLL
Noise-suppressed
receive clock
(1/1 clock mode)