HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 43

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Send data
1. Decode address
2. Put data on bus
3. WAIT inactive
End of cycle
WAIT active
Memory
Figure 1.15 Transmit DMA Operation (CPU mode 0)
Access memory
1. Put address on bus (A to A , BHE)
2. AS active
3. RD active
End of transfer
AS and RD inactive
Or start next cycle
Relinquish bus
Get bus
DMAC
0
SCA
If the number of bytes of data in TX
FIFO has dropped to the number set in
MSCI TX ready control register 0 (TRC0)
or less, and has not subsequently risen
to the number set in MSCI TX ready
control register 1 (TRC1) + 1 or greater
MSCI response
1. Read data
2. If the number of bytes of data in
23
TX FIFO after this transfer is equal to
or greater than the number set in MSCI
TX ready control register 1 (TRC1) + 1,
negate TXRDY (to inactivate the DMA
request)
DMA Request
TXRDY active
MSCI
Rev. 0, 07/98, page 27 of 453