HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 339

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Wait Control Register H (WCRH): Specifies the number of wait states to be inserted in a
memory cycle when the PAH area is accessed.
Bits 7 3: Reserved. These bits always read 0 and must be set to 0.
Bits 2 0 (PAHW2 PAHW0: PAH Area Wait): The functions of these bits are described
below.
PAHW2, PAHW1, PAHW0 = 0, 0, 0: Number of wait states = 0
PAHW2, PAHW1, PAHW0 = 0, 0, 1: Number of wait states = 1
PAHW2, PAHW1, PAHW0 = 0, 1, 0: Number of wait states = 2
PAHW2, PAHW1, PAHW0 = 0, 1, 1: Number of wait states = 3
PAHW2, PAHW1, PAHW0 = 1, 0, 0: Number of wait states = 4
PAHW2, PAHW1, PAHW0 = 1, 0, 1: Number of wait states = 5
PAHW2, PAHW1, PAHW0 = 1, 1, 0: Number of wait states = 6
PAHW2, PAHW1, PAHW0 = 1, 1, 1: Number of wait states = 7
Note that PAHW2, PAHW1, and PAHW0 are initialized to (1, 1, 1) at reset.
8.3
8.3.1
Wait states can be inserted between states T
WAIT line.
Operation
Wait State Insertion Using the WAIT Line
Bit name
Read/Write
Initial value
Note: Bits 7–3 are reserved. These bits always read 0 and must be set to 0.
—
—
7
0
—
—
6
0
—
2
—
5
0
and T
—
3
—
4
0
of states T
—
—
3
0
1
Rev. 0, 07/98, page 323 of 453
PAHW2 PAHW1
T
R/W
3
2
1
of a DMA bus cycle, using the
PAH area wait
R/W
1
1
PAHW0
R/W
0
1