HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 267

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

6.2.8
The DMA mode register (DMR), provided for each of channels 0, 1, 2, and 3, specifies DMA
transfer mode and number of DMA frames (single or multiple). This register also enables or
disables the frame end interrupt counter (FCT).
This register must be set in DMA initial state.
Bits 7–5: Reserved. These bits always read 0 and must be set to 0.
Bit 4 (TMOD: DMA Transfer Mode): Specifies the DMAC operation mode in either single-
block transfer mode or chained-block transfer mode as follows. This bit is reset to 0.
TMOD = 0: Specifies single-block transfer mode
TMOD = 1: Specifies chained-block transfer mode
Notes: 1.
Single-block
transfer mode
Chained-block
transfer mode
Read/Write
Initial value
DMA Mode Register (DMR)
DMA transfer mode
0:
1:
2.
Single-block transfer
Chained-block transfer
Reserved. When read, this bit is undefined and can be set to 0 or 1.
Reserved. These bits always read 0 and must be set to 0.
—
—
7
0
*2
—
—
6
0
*2
—
—
5
0
*2
Number of DMA frames
•
0:
1:
Frame end interrupt counter (FCT)
enable/disable
•
Set this bit to 0
•
0:
1:
Chained-block transfer
Single frame
Multi-frame
Single-block transfer
Chained-block transfer
Frame end interrupt counter (FCT) disabled
Frame end interrupt counter (FCT) enabled
TMOD
R/W
4
0
—
—
3
0
*2
R/W
Rev. 0, 07/98, page 251 of 453
—
NF
2
0
*1
CNTE
R/W
1
0
—
—
0
0
*2