HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 306

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Table 6.7
Register
Name
Register
updated by
the MPU
Number of
bits
Function
Role in
DMAC
operation
Register
update
Register
updated by
the MPU
Table 6.8 shows a typical MSCI-to-memory chained-block multi-frame transfer using four
descriptors and four buffers. In this example, after a transfer begins, CDA is updated and then the
CDA initial value is written to EDA since transfer is disabled when CDA and EDA are equal. As
a result, the write-enabled buffer size is maximized. In this example, the CDA and EDA values
match after frame 2 has been transferred (step 9). At this time, any additional transfer request is
disabled and interrupt DMIA is generated (if enabled).
Rev. 0, 07/98, page 290 of 453
Receive Buffer Length
(BFL)
Initialized before reception.
16
Indicates the buffer length
in bytes.
—
Under MPU control.
Initialized.
Control Registers Used in MSCI-to-Memory Chained-Block Transfer Mode
(reception) (cont)
Byte Count Register
(BCR)
Loaded with the start
address of the descriptor
indicating the buffer following
the last write buffer. When
releasing the buffer, this
register indicates the start
address of the descriptor for
the buffer following the one
being released.
16
Indicates the byte count of
the data remaining in the
buffer waiting to be written
to memory. Writing to this
register by the MPU is
prohibited.
When the contents of this
register equal 0000H, writing
to the current buffer stops.
The contents are
decremented each time
one byte or one word is
written. When the buffer
is switched, the BFL value
is loaded.
—
Buffer Address
Register (BAR)
When reception begins,
indicates the start
address of the descriptor
which indicates the buffer
to be written.
24
Indicates the system
memory address of the
data being loaded into
the buffer. Writing to this
register by the MPU is
prohibited.
When a transfer request
is issued, data is loaded
into the address specified
by this register.
The contents are
incremented each time
one byte or one word is
written. When the buffer
is switched, the next
buffer start address is
loaded.
—