HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 29

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

1.6.5
Register
Name
Destination
address
register L
(buffer
address
register L)*
Destination
address
register H
(buffer
address
register H)*
Destination
address
register B
(buffer
address
register B)*
Source
address
register L*
Source
address
register H*
Source
address
register B
(chain pointer
base)*
Current
descriptor
address
register L
Notes: 1. Parentheses indicate registers with different functions in single-block transfer mode and
1
2. These registers are not used in chained-block transfer mode. Avoid writing to these
2
2
1
1
1
DMA Registers Provided Separately for Channels 0 to 3
Symbol
DARL
(BARL)
DARH
(BARH)
DARB
(BARB)
SARL
SARH
SARB
(CPB)
CDAL
chained-block transfer mode. The name in parentheses applies in chained-block
transfer mode. See the register descriptions for details.
registers in chained-block transfer mode.
Chan-
nel 0
80H
81H
82H
86H
88H
CPU Modes 0 & 1
Chan-
nel 1
A0H
A1H
A2H
A4H
A5H
A6H
A8H
Chan-
nel 2
C0H
C1H
C2H
C6H
C8H
Chan-
nel 3
E0H
E1H
E2H
E4H
E5H
E6H
E8H
Address
Chan-
nel 0
81H
80H
83H
87H
89H
CPU Modes 2 & 3
Chan-
nel 1
A1H
A0H
A3H
A5H
A4H
A7H
A9H
Chan-
nel 2
C1H
C0H
C3H
C7H
C9H
Chan-
nel 3
E1H
E0H
E3H
E5H
E4H
E7H
E9H
MSB
Rev. 0, 07/98, page 13 of 453
Hardware Reset
Initial Value at
( : undefined)
LSB
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W