HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 338

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Wait Control Register M (WCRM): Specifies the number of wait states to be inserted in a
memory cycle when the PAM area is accessed.
Bits 7 3: Reserved. These bits always read 0 and must be set to 0.
Bits 2 0 (PAMW2 PAMW0: PAM Area Wait): The function of these bits are described
below.
PAMW2, PAMW1, PAMW0 = 0, 0, 0: Number of wait states = 0
PAMW2, PAMW1, PAMW0 = 0, 0, 1: Number of wait states = 1
PAMW2, PAMW1, PAMW0 = 0, 1, 0: Number of wait states = 2
PAMW2, PAMW1, PAMW0 = 0, 1, 1: Number of wait states = 3
PAMW2, PAMW1, PAMW0 = 1, 0, 0: Number of wait states = 4
PAMW2, PAMW1, PAMW0 = 1, 0, 1: Number of wait states = 5
PAMW2, PAMW1, PAMW0 = 1, 1, 0: Number of wait states = 6
PAMW2, PAMW1, PAMW0 = 1, 1, 1: Number of wait states = 7
Note that PAMW2, PAMW1, and PAMW0 are initialized to (1, 1, 1) at reset.
Rev. 0, 07/98, page 322 of 453
Bit name
Read/Write
Initial value
Note: Bit 7 to bit 3 are reserved. These bits always read 0 and must be set to 0.
—
—
7
0
—
—
6
0
—
—
5
0
—
—
4
0
—
—
3
0
PAMW2 PAMW1
R/W
2
1
PAM area wait
R/W
1
1
PAMW0
R/W
0
1