HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 218

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Message End Operation: During transmission, the MSCI recognizes the end of message when it
executes an end of message command. Also, the MSCI automatically assumes an end of message
for either a completed DMA-chained block transfer or an underrun error occurring when the
UDRNC bit of CTL is 1.
The last character to be transmitted is the first character written to the transmit buffer after an end
of message command is issued; it is the last character transferred in DMA-chained block transfer,
and is the character transmitted immediately before the underrun in underrun state.
Rev. 0, 07/98, page 202 of 453
During reception, CRC calculation is carried out on the 0-deleted data in the A, C, and I fields.
The CRC code check is completed when the last character in the I field enters the receive
buffer with the CRCCC bit of MD0 = 1. The error status is sent to the status FIFO associated
with the character before being set to the CRCE bit of ST2. When the CRCE bit is set to 1, an
interrupt request is generated (if enabled). When the CRCCC bit is 0, the CRCE bit is not set
to 1.
Overrun error
An overrun error occurs when the receive buffer is full when new data is transferred.
When an overrun error occurs, the new data overwrites the top stage of the receive buffer,
erasing the previous data. At the same time, the top stage of the status FIFO is overwritten
with the status (indicating an overrun) of the new data. The EOM bit is cleared as well when
the new data is written.
The OVRN bit of ST2 is set to 1 when the new data becomes ready to be read. This generates
an interrupt request is generated (if enabled).
Even if an overrun error occurs, subsequent characters are received normally. However, the
OVRN bit is not cleared even if the subsequent data causes no overrun error. It can be cleared
only when a 1 is written to the bit position or ST2 is reset.
Underrun error
An underrun error occurs when the transmit buffer is empty after data has been sent from the
transmit shift register.
When an underrun error occurs and abort transmission is enabled by the UDRNC bit of CTL,
the transmitter enters idle state after sending an abort. (The MSCI assumes an underrun error
when the transmit shift register and transmit buffer are both empty and an end of message
command has not been issued.) In other cases, the MSCI assumes that an underrun error is an
end of message and terminates the frame normally. Thus, the MSCI enters idle state after
sending FCS and a flag.
The UDRN bit of ST1 is set to 1 when an underrun error occurs. In this case, the transmit
buffer is not full, but the TXRDY bit of ST0 is not set to 1 as long as the UDRN bit remains 1.
This prevents the remaining data from being transmitted as a normal frame when an underrun
occurs during DMA transfer.
When the UDRN bit is set to 1, an interrupt request is generated (if enabled).