HD64570 HITACHI [Hitachi Semiconductor], HD64570 Datasheet - Page 215

• Manufacturer Part Number: HD64570
• Description: Serial Communications Adaptor
• Manufacturer: HITACHI [Hitachi Semiconductor]

Reception Operation: Figure 5.28 is the state transition diagram for reception in bit synchronous
mode.
Figure 5.27 State Transition Diagram for Transmission in Bit Synchronous HDLC Mode
transmit state
Opening flag
"TX reset" or
"channel reset"
issued in any state
Initialization by reset
Data remaining
in transmit buffer
UDRNC:
CRCCC:
EOM:
Note:
TX disable
state
1. Command names are enclosed in double quotation marks ("").
2. The state changes when character or pattern transmission is completed,
Underrun state control bit (control register (CTL) bit 5)
CRC calculation bit (mode register 0 (MD0) bit 2)
End of message command issued or completion of data transmission
signaled from the DMAC to MSCI during DMA chained-block transfer
After
transmission
except when the transmitter is reset.
2. "Abort transmission"
No data remaining
in transmit buffer
and "TX disable"
issued
Data remaining in
transmit buffer
and "EOM" not
issued
issued
1. Underrun state
Data remaining in transmit buffer after flag transmission
"TX enable" issued
and UDRNC = 0
transmit state
Character
Data still in
transmit
buffer after
abort sent
1. CRCCC = 1
2. Underrun state,
and "EOM" issued
CRCCC = 1, and UDRNC =1
No data remaining in transmit
buffer and "TX disable" not issued
1. CRCCC = 0
2. Underrun state,
Idle state
and "EOM" issued
CRCCC = 0, and UDRNC =1
transmit state
No data remaining in
transmit buffer after
abort transmission
Abort
FCS transmit
state
"Abort transmission"
issued
"Abort transmission"
issued several
times
Rev. 0, 07/98, page 199 of 453
After
transmission
"Abort transmission"
issued
transmit state
Closing flag
Transmit buffer
empty after flag
transmission