LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 11

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
1.4 Block diagram
UM10398
User manual
Fig 1.
CT32B0_MAT[3:0]
CT32B1_MAT[3:0]
CT16B0_MAT[2:0]
CT16B1_MAT[1:0]
DTR, DSR, CTS
(1) LQFP48 packages only.
(2) Not on LPC1112FDH20/102.
(3) All pins available on LQFP48 and HVQFN33 packages. CT16B1_MAT1 not available on TSSOP28/DIP28 packages.
(4) AD[7:0] available on LQFP48 and HVQFN33 packages. AD[5:0] available on TSSOP28/DIP28/HVQFN24packages. AD[4:0]
(5) All pins available on LQFP48 packages. RXD, TXD, DTR, CTS, RTS available on HVQFN 33 packages. RXD, TXD, CTS, RTS
CT32B0_CAP0
CT32B1_CAP0
CT16B0_CAP0
CT16B1_CAP0
DCD, RI, RTS
GPIO ports
PIO0/1/2/3
CT32B1_MAT3, CT16B1_CAP0, CT16B1_MAT[1:0], CT32B0_CAP0 not available on TSSOP20/SO20 packages.
CT16B1_MAT[1:0], CT32B0_CAP0 not available on the HVQFN24 package. XTALOUT not available on LPC1112FHN24.
available on TSSOP20/SO20 packages.
available on TSSOP28/DIP28 packages. RXD, TXD available on TSSOP20/SO20 packages.
LPC111x block diagram (LPC1100 and LPC1100L series)
RXD
TXD
(5)
(5)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
,
LPC1110/11/12/13/14
HIGH-SPEED
GPIO
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
16-bit COUNTER/TIMER 0
16-bit COUNTER/TIMER 1
system bus
UART
slave
CORTEX-M0
All information provided in this document is subject to legal disclaimers.
TEST/DEBUG
INTERFACE
SWD
ARM
Rev. 12 — 24 September 2012
Chapter 1: LPC111x/LPC11Cxx Introductory information
4/8/16/24/32 kB
slave
FLASH
AHB-LITE BUS
slave
AHB TO APB
BRIDGE
slave
1/2/4/8 kB
SRAM
POR
IRC
slave
XTALOUT
SYSTEM CONTROL
POWER CONTROL,
ROM
GENERATION,
10-bit ADC
I
IOCONFIG
2
FUNCTIONS
C-BUS
SPI1
SYSTEM
SPI0
WDT
PMU
(3)
XTALIN
CLOCK
clocks and
controls
(1)
(2)
RESET
002aae696
UM10398
© NXP B.V. 2012. All rights reserved.
CLKOUT
AD[7:0]
SCL
SDA
SCK0, SSEL0
MISO0, MOSI
SCK1, SSEL1
MISO1, MOSI
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