LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 301

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
16.7.2.4.5 Software control of pin CAN_TXD
16.7.3 CAN message handler
As soon the CAN bus is idle, the IF1 Registers are loaded into the shift register of the CAN
Core and the transmission is started. When the transmission has completed, the BUSY bit
is reset and the locked IF1 Registers are released.
A pending transmission can be aborted at any time by resetting the BUSY bit in the IF1
Command Request Register while the IF1 Registers are locked. If the CPU has reset the
BUSY bit, a possible retransmission in case of lost arbitration or in case of an error is
disabled.
The IF2 Registers are used as Receive Buffer. After the reception of a message the
contents of the shift register is stored into the IF2 Registers, without any acceptance
filtering.
Additionally, the actual contents of the shift register can be monitored during the message
transfer. Each time a read Message Object is initiated by writing the BUSY bit of the IF2
Command Request Register to ‘1’, the contents of the shift register is stored into the IF2
Registers.
In Basic mode the evaluation of all Message Object related control and status bits and of
the control bits of the IFx Command Mask Registers is turned off. The message number of
the Command request registers is not evaluated. The NEWDAT and MSGLST bits of the
IF2 Message Control Register retain their function, DLC3-0 will show the received DLC,
the other control bits will be read as ‘0’.
In Basic mode the ready output CAN_WAIT_B is disabled (always ‘1’)
Four output functions are available for the CAN transmit pin CAN_TXD:
The last two functions, combined with the readable CAN receive pin CAN_RXD, can be
used to check the CAN bus’ physical layer.
The output mode of pin CAN_TXD is selected by programming the Test Register bits TX1
and TX0 as described
Remark: The three test functions for pin CAN_TXD interfere with all CAN protocol
functions. The CAN_TXD pin must be left in its default function when CAN message
transfer or any of the test modes Loo-back mode, Silent mode, or Basic mode are
selected.
The Message handler controls the data transfer between the Rx/Tx Shift Register of the
CAN Core, the Message RAM and the IFx Registers, see
The message handler controls the following functions:
1. serial data output (default).
2. drives CAN sample point signal to monitor the CAN controller’s timing.
3. drives recessive constant value.
4. drives dominant constant value.
•
Data Transfer between IFx Registers and the Message RAM
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Section
16.6.1.6.
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
Figure
64.
UM10398
© NXP B.V. 2012. All rights reserved.
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