LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 446

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
28.4 Processor
UM10398
User manual
28.4.1.1 Processor modes
28.4.1.2 Stacks
28.4.1.3 Core registers
28.3.4 Cortex-M0 core peripherals
28.4.1 Programmers model
These are:
NVIC — The NVIC is an embedded interrupt controller that supports low latency interrupt
processing.
System Control Block — The System Control Block (SCB) is the programmers model
interface to the processor. It provides system implementation information and system
control, including configuration, control, and reporting of system exceptions.
System timer — The system timer, SysTick, is a 24-bit count-down timer. Use this as a
Real Time Operating System (RTOS) tick timer or as a simple counter.
This section describes the Cortex-M0 programmers model. In addition to the individual
core register descriptions, it contains information about the processor modes and stacks.
The processor modes are:
Thread mode — Used to execute application software. The processor enters Thread
mode when it comes out of reset.
Handler mode — Used to handle exceptions. The processor returns to Thread mode
when it has finished all exception processing.
The processor uses a full descending stack. This means the stack pointer indicates the
last stacked item on the stack memory. When the processor pushes a new item onto the
stack, it decrements the stack pointer and then writes the item to the new memory
location. The processor implements two stacks, the main stack and the process stack,
with independent copies of the stack pointer, see
In Thread mode, the CONTROL register controls whether the processor uses the main
stack or the process stack, see
always uses the main stack. The options for processor operations are:
Table 418. Summary of processor mode and stack use options
The processor core registers are:
Processor
mode
Thread
Handler
•
extensive debug capabilities.
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Used to
execute
Applications
Exception
handlers
Rev. 12 — 24 September 2012
Section
Stack used
Main stack or process stack
See
Main stack
28–28.4.1.3.7. In Handler mode, the processor
Section 28–28.4.1.3.7
Section
28.4.1.3.2.
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