LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 475

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.5.4.3.2 Operation
28.5.4.3.3 Restrictions
28.5.4.3.4 Condition flags
28.5.4.3.5 Examples
28.5.4.4.1 Syntax
28.5.4.4.2 Operation
28.5.4.4.3 Restrictions
28.5.4.4.4 Condition flags
28.5.4.4 LDR, PC-relative
LDR, LDRB, U, LDRSB and LDRSH load the register specified by Rt with either a word,
zero extended byte, zero extended halfword, sign extended byte or sign extended
halfword value from memory.
STR, STRB and STRH store the word, least-significant byte or lower halfword contained
in the single register specified by Rt into memory.
The memory address to load from or store to is the sum of the values in the registers
specified by Rn and Rm.
In these instructions:
These instructions do not change the flags.
Load register (literal) from memory.
LDR Rt, label
where:
Loads the register specified by Rt from the word in memory specified by label.
In these instructions, label must be within 1020 bytes of the current PC and word aligned.
These instructions do not change the flags.
•
•
STR R0, [R5, R1]
LDRSH R1, [R2, R3]
Rt is the register to load.
label is a PC-relative expression. See
Rt, Rn, and Rm must only specify R0-R7.
the computed memory address must be divisible by the number of bytes in the load or
store, see
Section
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
; and write to R1.
Rev. 12 — 24 September 2012
; Store value of R0 into an address equal to
; sum of R5 and R1
; specified by (R2 + R3), sign extend to 32-bits
28–28.5.3.4.
; Load a halfword from the memory address
Section
28–28.5.3.5.
UM10398
© NXP B.V. 2012. All rights reserved.
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